1. Field of the Invention
The present invention relates to a semiconductor device including a MOS transistor, and a method of manufacturing the semiconductor device.
2. Description of the Related Art
As an improved MOS transistor, a MOS transistor (Schottky source/drain transistor) that has source/drain regions with a Schottky junction (a Schottky source/drain structure) is known (Jakub Kedzierski, et al., IEDM Technical Digest, pp. 57-60, 2000). The source/drain regions of the transistor are conductive layers that contain a metal or a metal silicide, instead of impurity diffusion layers.
The Schottky source/drain transistor can reduce the parasitic resistance in the source/drain regions, and also can advantageously reduce the junction depth (the Schottky junction) of the source/drain regions.
Since impurity diffusion layers are not used for the source/drain regions, there is no need to perform a high temperature heating process to activate the impurity. Accordingly, the manufacturing process is greatly simplified, and as a result, the LSI manufacturing cost is reduced.
Further, as a Schottky barrier exists at the source edge, off current is suppressed, and, as a result, short channel effect is suppressed. Thereby, the device is easily miniaturized.
However, the conventional Schottky source/drain transistor has the following problems.
In the case of a usual transistor, source/drain regions are made of the same material (silicon) as channel region. Accordingly, there is no problem with the contact resistance between the channel region and the source/drain-regions.
On the contrary, in the case of the source/drain regions of the Schottky source/drain transistor, the source/drain regions are made of a different material from the channel region. Therefore, it is necessary to reduce the contact resistance between the channel region and the source/drain regions (the interface resistance Rc between the Si and the silicide).
As a solution for the problem, there is a source/drain material work function control technology. For example, a method using a metal or silicide (such as ErSi2) having a small work function for the source/drain regions of an nmOS and using a metal or silicide (such as PtSi) having a large work function for the source/drain regions of a PMOS is proposed.
Using the work function control method, a Schottky barrier of an n-channel MOS (NMOS) transistor can be made to be approximately 0.28 eV, and a Schottky barrier of a p-channel MOS (PMOS) transistor can be made to be approximately 0.22 eV. Accordingly, source/drain regions (metal-silicide source/drain) with relatively low Schottky contact resistance can be formed for both of the nmOS and PMOS.
In this manner, the value of the Schottky barrier can be reduced by the work function control method, though, the above mentioned values are still too large to obtain sufficiently high current. However, with the work function control method only, a further decrease in the Schottky barrier is difficult due to bad influence of Fermi-level pinning effects.
Further, a technique for reducing an interface resistance Rc by providing an extension (an impurity diffusion layer) in the Schottky junction is proposed. However, it is difficult to form a shallow extension with high impurity concentration in a very small device.